The present invention relates to a method for fabricating a semiconductor device and fabricating apparatus therefor, and in particular, to a method for fabricating a semiconductor device with extension regions connected with a source diffusion region and a drain diffusion region, and fabricating apparatus therefor.
Conventionally, in a process of forming a source diffusion region or a drain diffusion region for suppressing a short channel effect due to miniaturization of a MOS transistor, there is known a method in which offset sidewalls are formed on the side surfaces of a gate electrode, and ion implantation is performed by using the gate electrode and the sidewalls as masks, whereby a source diffusion region or a drain diffusion region is formed in a self-aligned manner.
For example, Japanese Patent-Application Laid-open No. 2003-100902 describes a method in which, by using offset sidewalls formed on the side surfaces of a gate electrode, a source diffusion region and a drain diffusion region, and extension regions of low concentration connected with the source diffusion region and the drain diffusion region, are formed through ion implantations performed in two stages.
Hereinafter, a conventional method for fabricating a MOS transistor with extension regions will be described with reference to drawings.
FIGS. 7A to 7C, 8A and 8B show sectional structures in the order of steps of a conventional method for fabricating a MOS transistor.
First, as shown in FIG. 7A, isolation films 102 are selectively formed on a semiconductor wafer 101 made of silicon, and p-type impurity ions are diffused in a region between the formed isolation films 102, to thereby form a well diffusion region 103. Then, on the semiconductor wafer 101, a silicon oxide film 104 and a poly-silicon film 105 are formed over the whole surface including the upper surfaces of the isolation films 102 and the well diffusion region 103.
Next, as shown in FIG. 7B, the poly-silicon film 105 and the silicon oxide film 104 are pattered in order, to thereby form a gate insulating film 104A from the silicon oxide film 104 and form a gate electrode 105A from the poly-silicon film 105. Then, on the semiconductor wafer 101, a first insulating film 106 made of silicon oxide is formed over the whole surface so as to surround the gate electrode 105A.
Next, as shown in FIG. 7C, first sidewalls 106A covering the side surfaces of the gate electrode 105A are formed by etching the first insulating film 106 from the top surface side, and n-type impurity ions are implanted through a low energy ion implantation using the gate electrode 105A and the first sidewalls as masks, to thereby form extension regions 107. Then, using the gate electrode 105A and the first sidewalls as masks, pocket regions 108 are formed by implanting (pocket implanting) p-type impurity ions through ion implantation in which an ion beam is tilted to the gate electrode 105A.
Here, the extension region 107 is a low concentration diffusion region connected with a source diffusion region or a drain diffusion region, and suppresses a short channel effect due to a miniaturization of a semiconductor device. The pocket region 108 is an impurity diffusion region of an opposite conductive type to the extension region 107, whereby it suppresses lateral spreading of a depletion region under the gate electrode 105A, and reduces a leakage current between the gate and the drain.
Next, as shown in FIG. 8A, on the semiconductor wafer 101, a second insulating film 109 made of silicon oxide is formed over the whole surface including the upper surfaces of the gate electrode 105A and the first sidewalls 106A.
Next, as shown in FIG. 8B, the second insulating film 109 is etched to thereby form second sidewalls 109A covering the sides of the first sidewalls 106A. Then, source/drain regions 110 made of n-type impurities are formed through ion implantation by using the second sidewalls 109A as masks.
According to the conventional method for fabricating a MOS transistor, the extension regions 107 and the source/drain regions 110 are formed in a self-aligned manner by using the first sidewalls 106A and the second sidewalls 109A as masks. Thereby, it is possible to form easily and securely a semiconductor device capable of suppressing a short channel effect due to miniaturization and reducing a leakage current between the gate and the drain.
In the conventional method for fabricating a MOS transistor, the step of forming the extension regions 107 needs to use an extremely low-energy ion beam. In general, a so-called batch-type ion implantation device is used, which device is so configured as to enable ion implantation to be performed collectively to a plurality of semiconductor wafers 101. In particular, an ion beam with low energy is difficult to be scanned by deflection, whereby ion implantation is performed to the whole surfaces of respective semiconductor wafers 101 by rotating and moving a wafer supporting board called a disk.
Hereinafter, a conventional batch-type ion implantation device will be described with reference to the drawings.
FIG. 9 is a perspective view showing the shape of a disk used for a conventional batch-type ion implantation device. As shown in FIG. 9, the conventional batch-type ion implantation device holds semiconductor wafers 101 to which ion implantation is performed, in a plurality of wafer holding areas 201a provided in the periphery of the circle disk 201. With this device, an ion beam 210 consisting of impurity ions to be implanted is irradiated to the semiconductor wafers 101, to thereby implant impurity ions to the semiconductor wafers 101.
The disk 201 is configured to be rotatable and movable by a rotation axis 202 and a scan axis 203. In FIG. 9, it is assumed that an extending direction of the rotation axis 202 is z axis, an extending direction of the scan axis 203 is y axis, and a direction vertical to the y axis and the z axis is x axis.
When implanting impurity ions over the whole surfaces of the semiconductor wafers 101 by using the conventional batch-type ion implantation device, the disk 201 is rotated about the rotation axis 202 at a high speed and the scan axis is moved reciprocally in the y direction. Thereby, impurity ions can be implanted to a plurality of semiconductor wafers 101 collectively and over the whole surfaces of respective wafers.
Further, in the conventional batch-type ion implantation device, a direction of implanting the ion beam 210 is fixed in a direction parallel to the z axis, and when adjusting the implanting angle of the ion beam 210 to the semiconductor wafers 101, the disk 201 is used to be tilted to the ion beam 210.
When forming the extension regions 107 shown in FIG. 7C by using the batch-type ion implantation device in FIG. 9, a method in which the ion beam 210 is implanted at once vertically to the semiconductor wafers 101, or a method in which the ion beam 210 is dividedly implanted four times from four directions by tilting the ion beam 210 to the semiconductor wafers 101, is generally used.
However, with the aforementioned conventional methods for fabricating a semiconductor device, it is difficult to surely form the extension regions 107, formed on the sides of the gate electrode 105, so as to be symmetrical to the gate electrode 105A on the both sides thereof, whereby a problem of asymmetry of the MOS transistor may arise.
Such an asymmetry of the MOS transistor is caused since, when forming the extension regions 107 using the conventional batch-type ion implantation device, the implantation angles of the ion beam 210 differs at the center and at the periphery of the semiconductor wafer 101 even though the angle of the ion beam 210 is set to be a certain value.
Implantation angles of the ion beam and the asymmetry of the MOS transistor will be described below with reference to the drawings.
FIG. 10A to 10C are illustrations explaining the angular relationships defined by the semiconductor wafer 101 and the ion beam 210 in the conventional batch-type ion implantation device. In FIGS. 10A to 10C, the disk 201 is expressed linearly for convenience of explanation. Further, in FIGS. 10A to 10C, an x axis, a y axis and a z axis conform to the x axis, the y axis and the z axis in FIG. 9, respectively.
As shown in FIG. 10A, in the disk 201, a wafer holding area 201a is provided to be tilted at a certain angle (cone angle A) to the rotation surface of the disk 201. The cone angle A is fixed at a certain value for each batch-type ion implantation device such that the semiconductor wafer 101 may be easily held by the wafer holding area 201a when the disk 201 rotates about the rotation axis 202.
Further, as shown in FIGS. 10B and 10C, a first jyro angle B1 and a second jyro angle B2 of the disk 201 can be set to be desired values, whereby the angle of the semiconductor wafers 101 to the ion beam 210 can be adjusted. In FIGS. 10B and 10C, cases where the first jyro angle B1 and the second jyro angle b2 are 0° (that is, in the initial state where the disk 201 is disposed in parallel with the xy plane) are shown by dotted lines. The first jyro angle B1 is such an angle that the disk 201 rotates about the rotation axis 202 from the initial state in the y axis direction, and the second jyro angle B2 is such an angle that the disk 201 rotates in the y axis direction.
FIGS. 11A to 11C are illustrations explaining implantation angles of the ion beam 210 in the conventional batch-type ion implanting device. As shown in FIG. 11A and 11B, an angle defined by the semiconductor wafer 101 and the ion beam 210 is expressed by two angles (that is, tilt angle T1 and twist angle T2). The tilt angle T1 is defined by the normal (a line indicated by the dotted line in FIG. 11A) of the semiconductor wafer 101 and the ion beam 210, and the twist angle T2 is defined by, assuming that a line linking a notch 110a showing the crystal orientation of the semiconductor wafer 101 and the center of the semiconductor wafer 101 is the reference line, the reference line and a projection line 210a showing the projection of the ion beam 201 to the semiconductor wafer 101.
Further, as shown in FIG. 1C, when the ion beam is irradiated to a point P rotated by a rotation angle C from the center of the semiconductor wafer 101 by rotating the disk 201 about the rotation axis 202, assuming that a line linking the center of the semiconductor wafer 101 and the center of the disk 201 is the reference line and that a vertical leg down from the point P to the reference line is a point Q, the rotation angle C is expressed as follows by using a distance R1 from the center of the semiconductor wafer 101 to the point Q, and a distance R2 from the point P to the point Q:C=tan−1(R2/R1)   (1)Then, at the point P, the tilt angle T1 and the twist angle T2 are expressed as follows:T1=cos−1{cos(B1−A)cos B2 cos A+sin B2 sin A sin C−sin(B1−A)cos B2 sin A cos C}  (2)T2=tan−1(k/h)   (3)
provided that, in the equation (3),k=sin B2 cos C+sin(B1−A)cos B2 sinh=cos(B1−A)cos B2 sin C+sin(B1−A)cos B2 cos A cos C−sin B2 cos A sin C
As obvious from the equations (2) and (3), the tilt angle T1 and the twist angle T2 are functions of the rotation angle C, whereby their values change corresponding to the distance R2 vertical to the reference line linking the center of the disk 201 and the center of the semiconductor wafer.
FIG. 12 is a graph showing the relationship between the distance R2 from the center of the semiconductor wafer and the implantation angle of the ion beam. In FIG. 12, the lateral axis shows the distance R2 from the reference line, linking the center of the disk 201 and the center of the semiconductor wafer 101, to the irradiating position of the ion beam, and the positive and negative symbols indicate directions to the reference line. The vertical axis shows the implantation angle (tilt angle T1 and twist angle T2) of the ion beam.
As shown in FIG. 12, although the tilt angle T1 and the twist angle T2 are set to be 0° at the center (R2=0) of the semiconductor wafer 101, it is obvious that the tilt angle T1 and the twist angle T2 change as they move away from the center of the semiconductor wafer 101. In this way, although the desired implantation angle has been set at the center of the semiconductor wafer 101, ion implantation is performed at an implantation angle different from the set implantation angle at the periphery of the semiconductor wafer 101.
Next, an influence of the shift in the implantation angle of the ion beam on the asymmetry of the MOS transistor will be described with reference to the drawings.
Here, assuming that in the two source/drain regions 110 formed on both sides of the gate electrode 105A, a drain current, in a case of applying a certain forward bias to respective regions so that one becomes a source region and the other becomes a drain region, is IDS1, and a drain current, in a case of applying a reverse bias, is IDS2, the asymmetry of the source/drain can be measured as (IDS1−IDS2)/IDS1.
FIG. 13 shows measurement values of the asymmetry of the source/drain as the distribution in the semiconductor wafer 101, when a plurality of MOS transistors with extension regions 107 are formed by using the batch-type ion implantation device shown in FIG. 9. In FIG. 13, a numeral value in a square in the semiconductor wafer 101 is a representative value showing the asymmetry of the source/drain of each MOS transistor disposed at a region where the square is located, and a mark of x or triangle attached on the upper right of each numeral value indicates that the value does not satisfy the asymmetry standard of the source/drain.
As shown in FIG. 13, the asymmetry of the source/drain increases from the center of the semiconductor wafer 101 to the periphery thereof. In recent years, it is required that the asymmetry of the source/drain is 3% or less, so this Figure shows that most parts in the periphery of the semiconductor wafer 101 do not meet the standard.
As described above, it is obvious that the asymmetry of the source/drain increases, as it moves away from the center of the semiconductor wafer 101, that is, as the shifted amounts of the tilt angle T1 and the twist angle T2 from the set values increase.
In order to improve the asymmetry of the source/drain, there has been tried a method in which the tilt angle T1 is set to be larger than 0° in the step of forming the extension regions 107, and implantations are performed from four directions by changing the twist angle T2.
FIGS. 14A and 14B show the relationship between the changing amount of the ion beam implantation angle and the distance from the center of the semiconductor wafer 101, when changing the set value of the twist angle T2 in the conventional batch-type ion implantation device. FIG. 14A shows the relationship between the distance from the center of the semiconductor wafer 101 and the changing amount of the tilt angle T1, and FIG. 14B shows the relationship between the distance from the center of the semiconductor wafer 101 and the changing amount of the twist angle T2. In FIGS. 14A and 14B, the tilt angle T1 at the center of the semiconductor wafer 101 is set to be about 7°.
As shown in FIGS. 14A and 14B, when changing the twist angle T2 from 0° to 90°, 180° and 270°, the tilt angle T1 changes in great amount in the periphery of the semiconductor wafer 101 when the twist angle T2 is 90° and 270°, in particular. In the case of the tilt angle being 7°, if the values of the first jyro angle B1 and the second jyro angle B2 are (B1, B2)=(7°, 0°), the twist angle T2 is 0°, if (B1, B2)=(0°, 7°), the twist angle T2 is 90°, if (B1, B2)=(−7°, 0°), the twist angle T2 is 180°, and if (B1, B2)=(0°, −7°), the twist angle T2 is 270°. Accordingly, the changing amount of the tilt angle T1 increases as the absolute value of the second jyro angle B2 increases.
As described above, even when performing ion implantations from four directions by changing the twist angle T2, the implantation angle, of the ion beam at the periphery of the semiconductor wafer 101 may change in great amount, depending on the value of the jyro angle.
FIGS. 15A and 15B show positioning relationships between the gate electrode 105A and the extension regions 107 in the case where the extension regions 107 are formed by performing the ion implantations four times as described above. FIG. 15A shows a MOS transistor at the center of the semiconductor wafer 101, and FIG. 15B shows a MOS transistor at the periphery of the semiconductor wafer 101. In FIGS. 15A and 15B, each numeral shown on the upper side indicates a distance from a side surface of the gate electrode 105A to the edge of the extension region 107. Further, the twist angle is changed by 90° sequentially, from 0° to 90°, 180° and 270° in the first to the fourth ion implantations.
As shown in FIG. 15A, at the center of the semiconductor wafer 101, the extension regions are formed symmetrical to the gate electrode 105A, from the first layered extension regions 107a formed by the first ion implantation to the fourth layered extension regions 107d formed by the fourth ion implantation. However, as shown in FIG. 15B, at the periphery of the semiconductor wafer 101, although the first layered extension regions 107a and the second layered extension regions 107b, formed by the first and the second ion implantations, respectively, are formed symmetrical to the gate electrode 105A, the third layered extension regions 107c and the fourth layered extension regions 107d, formed by the third and fourth ion implantations, respectively, are formed asymmetrical to the gate electrode 105A.
In this way, even though the ion implantations are performed from four directions by changing the twist angle T2, it is obvious that the extension regions 107 cannot be formed symmetrical to the gate electrode 105A on the both sides thereof.
Further, as another method for improving the asymmetry of the source/drain, there is known a method in which the first sidewalls 106A, serving as masks when forming the extension regions 107, are filmed.
FIG. 16 is a graph showing the relationship between the distance from the center of the semiconductor wafer and the asymmetry of the source/drain when the offset film thickness of the first sidewall 106A (that is, the width of the bottom surface of the first sidewall 106 shown in FIG. 8B) is changed in the conventional method for fabricating a semiconductor device.
As shown in FIG. 16, as the offset film thickness of the first sidewall 106A increases, the asymmetry of the source/drain at the periphery of the semiconductor wafer 101 also increases. In order to make the asymmetry of the source/drain be 3% or less even at the periphery of the semiconductor wafer 101, the offset film thickness of the first sidewall 106A should be 3 nm or less, according to the Figure.
However, as the offset film thickness of the first sidewall 106A decreases, no effect of forming the first sidewalls 106A is achieved, whereby the extension regions 107 and the pocket regions 108 are not formed at the desired positions, and such effects as suppression of a short channel effect, reduction in gate leakage current, or the like cannot be achieved.
As described above, according to the conventional method for fabricating a semiconductor device, the implantation angle of the impurity ions changes in the wafer surface in the step of forming the extension regions using a batch-type ion implantation device, whereby the extension regions cannot be formed symmetrical to the gate electrode, causing the asymmetry of the source/drain. Further, even if performing ion implantations from four directions with the tilt angle being greater than 0° in order to solve the asymmetry of the source/drain, the tilt angle and the twist angle are shifted from the set values at the periphery of the wafer, whereby it is impossible to realize MOS transistors having fine symmetry of the source/drain with high yield.